This application claims the priority benefit of Taiwan application serial no. 90119204, filed Aug. 7, 2001.
1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for programming and erasing data in a ROM with a silicon-ONO-silicon (SONOS) structure, which is a p-channel NROM having two bits in one memory cell.
2. Description of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today with various applications. For example, as the function of a microprocessor is more and more powerful, it usually need more software programs to perform these functions. And then, it needs a lot of memory to store all the programs and related information.
In order to increase the memory size, the dimension of the memory devices is greatly reduced. However, for the rather conventional memory structure, each memory cell can only serve as one bit for storing information.
Recently, a type of memory structure, so called an N-channel silicon-Oxide/Nitride/Oxide-silicon (SONOS) ROM, that is also called N-channel NROM, has been introduced, where the ONO layer serves as charge trapping layer to store two bit data. The N-channel SONOS ROM allows one memory cell to have two bits during writing data but the data cannot erased bit by bit. A conventional N-channel NROM and its operation for writing data is described in FIG. 1.
In FIG. 1, a substrate 100 is provided. An oxide/nitride/oxide (ONO) layer 110 is formed on the substrate 100, where the ONO layer serving as a trapping layer 110 includes an oxide layer 104, a nitride layer 106, and another oxide layer 108. Two N+ doped regions 102a, 102b are formed in the substrate 100 at each side of the trapping layer 110. A polysilicon gate layer 112 doped with N-type dopants is formed on the trapping layer 110. For this structure of the memory cell, it has an I-V curve as shown in FIG. 2. When a bias of 9 volts is applied to the gate layer 112, a hot electrons would occur.
When the memory cell as shown in FIG. 1 is to programmed with data or the data is to be erased, it can be achieved by setting proper the biases for Vd, Vg, Vs, and VB. If the doped region 102a be set to be drain region and the doped region 102b is set to be source region, the bias relation between programming/erasing (P/E) operation is illustrated as table 1.
When the biases are set to be Vg=Vd=9V and Vs=VB=0V, hot electrons are generated and then are trapped inside the nitride layer 106 near the drain region 102a as shown in a shaded area 114. When the data is to be erased, the hot electrons should be removed away. Usually, a band to band hot carrier mechanism is used to erase the data. The gate electrode and the substrate are grounded. The drain region is applied with a bias of 9V. The source region is set to be floating. In this manner, the hot holes are generated and driven into the ONO layer, whereby the hot electrons are annihilated away. However, the electrons stored in adjacent cell would be affected during erasing. This causes that the erasing operation can only erases a block of data. There is no way to erase a single bit. In other words, a single bit operation is not possible during erasing.
Alternatively, if the doped region 102a and the doped region 102b are serving as a source region and a drain region in reverse order, another bit could be formed at the opposite side of the nitride layer 106. This allows two bits in one cell. However, the erasing operation is also in block operation.
For a P-channel NROM that is similar to an N-channel NROM but the doped type is different. For the conventional operation method, the Fowler-Nordheim (F-N) tunneling mechanism is used to write and erase data. The electrons generated under the F-N tunneling mechanism are not localized and flow to the whole cell. Therefore, it has the memory function with only one bit in one cell.
In the foregoing NROM, the conventional operation to operate P/E function still cannot achieve a complete single bit operation.
The invention provides an operation method on an P-channel SONOS memory device, so that a single bit operation can be achieved.
As embodied and broadly described herein, the invention provides a method to perform an P/E operation on a P-channel SONOS memory device. The method includes providing a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. While one of the two doped regions is set to be a drain region, the other one of the two doped regions serves as a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative bias, and the source region and the substrate are applied with a grounded voltage. The first negative voltage is sufficient to drive hot electrons into a trapping layer. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative bias in absolute value. In the mean time, the drain region is applied with the a third negative bias and the substrate are applied with a grounded voltage. The third negative bias is larger than second negative bias in absolute value, so that the bias difference is sufficient to cause the hot electrons to flow into the trapping layer.
In the foregoing, the operation can be repeated but the source region and the drain region are reversed, whereby the P/E action is operated with respect to another bit in the same cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.